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"2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic ..."

Dinesh Somasekhar et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523163

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  dblp key:
  - conf/isscc/SomasekharYALKHRKBDK08
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  - https://dblp.org/rec/conf/isscc/SomasekharYALKHRKBDK08
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi:
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC 2008: 274-275

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