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"Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning."

Tariq B. Ahmad, Maciej J. Ciesielski (2014)

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DOI: 10.1109/ISVLSI.2014.47

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/isvlsi/AhmadC14
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  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/AhmadC14
Tariq B. Ahmad, Maciej J. Ciesielski:
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. ISVLSI 2014: 619-624

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