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"A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS."

Kunzhi Yu et al. (2012)

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DOI: 10.1109/MWSCAS.2012.6292175

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-27

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  dblp key:
  - conf/mwscas/YuWMZZW12
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  - https://dblp.org/rec/conf/mwscas/YuWMZZW12
Kunzhi Yu, Ziqiang Wang, Xuan Ma, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS. MWSCAS 2012: 936-939

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