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"Verification of FPGA Layout Generators in Higher-Order Logic."

Oliver Pell (2006)

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DOI: 10.1007/S10817-006-9039-9

access: closed

type: Journal Article

metadata version: 2020-09-02

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Oliver Pell:
Verification of FPGA Layout Generators in Higher-Order Logic. J. Autom. Reason. 37(1-2): 117-152 (2006)

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