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"High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs."

Muzaffar Rao et al. (2016)

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DOI: 10.1142/S0218126616500699

access: closed

type: Journal Article

metadata version: 2021-01-15

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  dblp key:
  - journals/jcsc/RaoNGM16
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  persistent URL:
  - https://dblp.org/rec/journals/jcsc/RaoNGM16
Muzaffar Rao, Thomas Newe, Ian Andrew Grout, Avijit Mathur:
High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs. J. Circuits Syst. Comput. 25(7): 1650069:1-1650069:13 (2016)

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