"Area-efficient architectures for double precision multiplier on FPGA, with ..."

Manish Kumar Jaiswal, Ray C. C. Cheung (2013)

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DOI: 10.1016/J.MEJO.2013.02.021

access: closed

type: Journal Article

metadata version: 2020-02-22

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Manish Kumar Jaiswal, Ray C. C. Cheung:
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectron. J. 44(5): 421-430 (2013)

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