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"Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency ..."
Fazal Hameed, Lars Bauer, Jörg Henkel (2016)
- Fazal Hameed, Lars Bauer, Jörg Henkel:
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 651-664 (2016)
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