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"A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for ..."

Jianhui Wu et al. (2014)

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DOI: 10.1109/TCSII.2014.2304893

access: closed

type: Journal Article

metadata version: 2020-05-27

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Jianhui Wu, Jiafeng Zhu, YingCheng Xia, Na Bai:
A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 61-II(4): 264-268 (2014)

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