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"Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for ..."

Ashoka Visweswara Sathanur et al. (2011)

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DOI: 10.1109/TVLSI.2009.2035448

access: closed

type: Journal Article

metadata version: 2023-09-30

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Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 469-482 (2011)

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