"A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type ..."

Deeksha Verma et al. (2021)

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DOI: 10.1109/ACCESS.2021.3115601

access: open

type: Journal Article

metadata version: 2021-11-03

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Deeksha Verma, Behnam Samadpoor Rikan, Khuram Shehzad, Sung Jin Kim, Danial Khan, Venkatesh Kommangunta, Syed Adil Ali Shah, YoungGun Pu, Sang-Sun Yoo, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee:
A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration. IEEE Access 9: 133143-133155 (2021)

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