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"Design and implementation of low-power, high-speed, reliable and secured ..."

Swati G. Mavinkattimath et al. (2024)

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DOI: 10.1016/J.BSPC.2023.105554

access: closed

type: Journal Article

metadata version: 2024-01-13

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Swati G. Mavinkattimath, Rajashri Khanai, Dattaprasad Torse, Nalini Iyer:
Design and implementation of low-power, high-speed, reliable and secured Hardware Accelerator using 28 nm technology for biomedical devices. Biomed. Signal Process. Control. 88(Part B): 105554 (2024)

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