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"The hierarchical logic schematic capture."

Sanjaya K. Saxena, Sanjiv Saxena, Rao V. S. Malladi (1987)

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DOI: 10.1016/0097-8493(87)90021-5

access: closed

type: Journal Article

metadata version: 2020-02-19

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Sanjaya K. Saxena, Sanjiv Saxena, Rao V. S. Malladi:
The hierarchical logic schematic capture. Comput. Graph. 11(2): 87-93 (1987)

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