"Formal Verification of VHDL Descriptions in the Prevail Environment."

Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem (1992)

> Home

Details and statistics

DOI: 10.1109/54.143145

access: closed

type: Journal Article

metadata version: 2024-05-07

- view
  authority control:
- export record
  dblp key:
  - journals/dt/BorrionePS92
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/dt/BorrionePS92
Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem:
Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Des. Test Comput. 9(2): 42-56 (1992)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.