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"A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line ..."

Yandong Luo et al. (2022)

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DOI: 10.1109/JETCAS.2022.3177577

access: closed

type: Journal Article

metadata version: 2023-08-28

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Yandong Luo, Sourav Dutta, Ankit Kaul, Sung Kyu Lim, Muhannad S. Bakir, Suman Datta, Shimeng Yu:
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 445-457 (2022)

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