"A pure hardware-driven scheduler for enhancing bank-level parallelism in a ..."

Dongliang Xue, Linpeng Huang, Chentao Wu (2020)

> Home

Details and statistics

DOI: 10.1016/J.FUTURE.2020.01.047

access: closed

type: Journal Article

metadata version: 2020-04-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/fgcs/XueHW20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/fgcs/XueHW20
Dongliang Xue, Linpeng Huang, Chentao Wu:
A pure hardware-driven scheduler for enhancing bank-level parallelism in a persistent memory controller. Future Gener. Comput. Syst. 107: 383-393 (2020)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.