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"Design and theoretical analysis of a clock jitter reduction circuit using ..."
Kiichi Niitsu et al. (2019)
- Kiichi Niitsu, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. IEICE Electron. Express 16(13): 20190218 (2019)
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