"Design Optimization of a High-Speed, Area-Efficient and Low-Power ..."

Shoichi Masui et al. (2005)

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DOI: 10.1093/IETELE/E88-C.4.576

access: closed

type: Journal Article

metadata version: 2020-04-11

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Shoichi Masui, Kenji Mukaida, Masahiko Takenaka, Naoya Torii:
Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm. IEICE Trans. Electron. 88-C(4): 576-581 (2005)

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