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"A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme."

Go Matsukawa et al. (2015)

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DOI: 10.1587/TRANSELE.E98.C.333

access: closed

type: Journal Article

metadata version: 2024-03-11

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  dblp key:
  - journals/ieicet/MatsukawaNSOKSY15
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/MatsukawaNSOKSY15
Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. IEICE Trans. Electron. 98-C(4): 333-339 (2015)

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