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"Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, ..."

Hiroshi Nakamura et al. (2013)

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DOI: 10.1587/TRANSELE.E96.C.404

access: closed

type: Journal Article

metadata version: 2024-03-22

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  - https://dblp.org/rec/journals/ieicet/NakamuraWOUAKN13
Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki:
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. 96-C(4): 404-412 (2013)

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