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"Acceleration of Test Generation for Sequential Circuits Using Knowledge ..."

Masato Nakasato et al. (2007)

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DOI: 10.1093/IETISY/E90-1.1.296

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/NakasatoOSF07
Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara:
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Trans. Inf. Syst. 90-D(1): 296-305 (2007)

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