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"Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield ..."

Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee (2011)

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DOI: 10.1587/TRANSFUN.E94.A.706

access: closed

type: Journal Article

metadata version: 2020-04-11

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  dblp key:
  - journals/ieicet/TsaiKL11
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/TsaiKL11
Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee:
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 706-716 (2011)

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