"A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory ..."

Yasue Yamamoto et al. (2007)

> Home

Details and statistics

DOI: 10.1093/IETELE/E90-C.5.1129

access: closed

type: Journal Article

metadata version: 2024-02-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ieicet/YamamotoSKNSAKY07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/YamamotoSKNSAKY07
Yasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi:
A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. IEICE Trans. Electron. 90-C(5): 1129-1137 (2007)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.