"Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout ..."

Shusuke Yoshimoto et al. (2012)

Details and statistics

DOI: 10.1587/TRANSELE.E95.C.1675

access: closed

type: Journal Article

metadata version: 2024-03-11

a service of  Schloss Dagstuhl - Leibniz Center for Informatics