"A comparative study on formal verification techniques to verify large ..."

Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita (2026)

> Home

Details and statistics

DOI: 10.1016/J.VLSI.2025.102606

access: closed

type: Journal Article

metadata version: 2026-01-01

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/integration/KumarSF26
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/integration/KumarSF26
Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita:
A comparative study on formal verification techniques to verify large integer multiplier circuits. Integr. 107: 102606 (2026)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.