"AiTO: Simultaneous gate sizing and buffer insertion for timing ..."

Hongxi Wu et al. (2024)

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DOI: 10.1016/J.VLSI.2024.102211

access: closed

type: Journal Article

metadata version: 2024-10-06

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Hongxi Wu, Zhipeng Huang, Xingquan Li, Wenxing Zhu:
AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL. Integr. 98: 102211 (2024)

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