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"Transistor Sizing of Logic Gates to Maximize Input Delay Variability."

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell (2006)

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DOI: 10.1166/JOLPE.2006.014

access: closed

type: Journal Article

metadata version: 2020-05-22

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  - journals/jolpe/RajaAB06
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  - https://dblp.org/rec/journals/jolpe/RajaAB06
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electron. 2(1): 121-128 (2006)

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