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"Data-path unrolling with logic folding for area-time-efficient FPGA-based ..."

Siew-Kei Lam et al. (2019)

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DOI: 10.1007/S11554-017-0725-0

access: closed

type: Journal Article

metadata version: 2020-06-18

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  - https://dblp.org/rec/journals/jrtip/LamLWCJ19
Siew-Kei Lam, Teck Chuan Lim, Meiqing Wu, Bin Cao, Bhavan A. Jasani:
Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector. J. Real Time Image Process. 16(6): 2147-2158 (2019)

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