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"Chip size estimation for SOC design space exploration."

Hartwig Jeschke (2007)

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DOI: 10.1016/J.SYSARC.2007.01.012

access: closed

type: Journal Article

metadata version: 2020-05-19

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Hartwig Jeschke:
Chip size estimation for SOC design space exploration. J. Syst. Archit. 53(10): 764-776 (2007)

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