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"A high performance 0.35-μm 3.3-V BiCMOS technology optimized for ..."

Jashojiban Banik et al. (1996)

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DOI: 10.1109/4.540053

access: closed

type: Journal Article

metadata version: 2022-07-26

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  - journals/jssc/BanikWGY96
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  - https://dblp.org/rec/journals/jssc/BanikWGY96
Jashojiban Banik, Keng L. Wong, George L. Geannopoulos, Chung Y. Joseph Yip:
A high performance 0.35-μm 3.3-V BiCMOS technology optimized for product porting from a 0.6-μm 3.3-V BiCMOS technology. IEEE J. Solid State Circuits 31(10): 1437-1442 (1996)

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