BibTeX record journals/jssc/ChenCCPWLLY09

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@article{DBLP:journals/jssc/ChenCCPWLLY09,
  author    = {Yen{-}Huei Chen and
               Gary Chan and
               Shao{-}Yu Chou and
               Hsien{-}Yu Pan and
               Jui{-}Jen Wu and
               Robin Lee and
               Hung{-}Jen Liao and
               Hiroyuki Yamauchi},
  title     = {A 0.6 {V} Dual-Rail Compiler {SRAM} Design on 45 nm {CMOS} Technology
               With Adaptive {SRAM} Power for Lower VDD{\_}min VLSIs},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {44},
  number    = {4},
  pages     = {1209--1215},
  year      = {2009},
  url       = {https://doi.org/10.1109/JSSC.2009.2014208},
  doi       = {10.1109/JSSC.2009.2014208},
  timestamp = {Sun, 30 Aug 2020 00:12:25 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/ChenCCPWLLY09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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