"An all-digital phase-locked loop (ADPLL)-based clock recovery circuit."

Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee (1999)

Details and statistics

DOI: 10.1109/4.777104

access: closed

type: Journal Article

metadata version: 2022-07-05

a service of  Schloss Dagstuhl - Leibniz Center for Informatics