"A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM."

Yoshihisa Iwata et al. (1995)

> Home

Details and statistics

DOI: 10.1109/4.475702

access: closed

type: Journal Article

metadata version: 2023-05-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/IwataISNOMIWANMM95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/IwataISNOMIWANMM95
Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto:
A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. IEEE J. Solid State Circuits 30(11): 1157-1164 (1995)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.