"A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS ..."

Hyun-Woo Lee et al. (2012)

> Home

Details and statistics

DOI: 10.1109/JSSC.2012.2191027

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/LeeCSKKKKJKPKKCRCKKCC12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/LeeCSKKKKJKPKKCRCKKCC12
Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. IEEE J. Solid State Circuits 47(6): 1436-1447 (2012)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.