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"Physical design guides for substrate noise reduction in CMOS digital circuits."

Makoto Nagata et al. (2001)

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DOI: 10.1109/4.910494

access: closed

type: Journal Article

metadata version: 2022-04-09

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Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata:
Physical design guides for substrate noise reduction in CMOS digital circuits. IEEE J. Solid State Circuits 36(3): 539-549 (2001)

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