"A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line ..."

Ryu Ogiwara et al. (2000)

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DOI: 10.1109/4.839914

access: closed

type: Journal Article

metadata version: 2022-04-13

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Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka:
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. IEEE J. Solid State Circuits 35(4): 545-551 (2000)

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