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ORCID"An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating ..."
Suneui Park et al. (2022)
- Suneui Park
, Seojin Choi, Seyeon Yoo, Yoonseo Cho, Jaehyouk Choi:
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. IEEE J. Solid State Circuits 57(9): 2829-2840 (2022)
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