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"A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip."

Takao Watanabe et al. (1997)

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DOI: 10.1109/4.568823

access: closed

type: Journal Article

metadata version: 2022-07-07

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  - https://dblp.org/rec/journals/jssc/WatanabeFYTASTS97
Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome:
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. IEEE J. Solid State Circuits 32(5): 635-641 (1997)

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