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"Performance effects of pipeline architecture on an FPGA-based binary32 ..."
Xianyang Jiang et al. (2013)
- Xianyang Jiang, Peng Xiao, Meikang Qiu, Gaofeng Wang:
Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier. Microprocess. Microsystems 37(8-D): 1183-1191 (2013)
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