"Novel high-speed reconfigurable FPGA architectures for EMD-based image ..."

K. Sathish Shet et al. (2019)

> Home

Details and statistics

DOI: 10.1007/S11042-019-7187-2

access: closed

type: Journal Article

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/mta/ShetAHG19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mta/ShetAHG19
K. Sathish Shet, A. R. Aswath, M. C. Hanumantharaju, Xiao-Zhi Gao:
Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography. Multim. Tools Appl. 78(13): 18309-18338 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.