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"A Scheme to Design Concurrent Error Detection Techniques for the Fast ..."

Ricardo Gonzalez-Toral et al. (2018)

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DOI: 10.1109/TC.2018.2792445

access: closed

type: Journal Article

metadata version: 2022-07-21

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  persistent URL:
  - https://dblp.org/rec/journals/tc/Gonzalez-ToralR18
Ricardo Gonzalez-Toral, Pedro Reviriego, Juan Antonio Maestro, Zhen Gao:
A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs. IEEE Trans. Computers 67(7): 1039-1045 (2018)

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