"Test pattern generation and clock disabling for simultaneous test time and ..."

Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee (2003)

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DOI: 10.1109/TCAD.2002.807890

access: closed

type: Journal Article

metadata version: 2020-09-24

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Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee:
Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 363-370 (2003)

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