"An Incremental Placement Flow for Advanced FPGAs With Timing Awareness."

Zhifeng Lin et al. (2022)

> Home

Details and statistics

DOI: 10.1109/TCAD.2021.3120070

access: closed

type: Journal Article

metadata version: 2022-09-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/LinXZWYC22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/LinXZWYC22
Zhifeng Lin, Yanyue Xie, Peng Zou, Sifei Wang, Jun Yu, Jianli Chen:
An Incremental Placement Flow for Advanced FPGAs With Timing Awareness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3092-3103 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.