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"Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs."

Chiao-Ling Lung et al. (2013)

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DOI: 10.1109/TCAD.2013.2245375

access: closed

type: Journal Article

metadata version: 2022-12-13

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Chiao-Ling Lung, Yu-Shih Su, Hsih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang:
Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 1100-1109 (2013)

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