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"Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping."

Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic (2006)

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DOI: 10.1109/TCAD.2006.882119

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - journals/tcad/ManohararajahBV06
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  - https://dblp.org/rec/journals/tcad/ManohararajahBV06
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic:
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2331-2340 (2006)

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