"FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture."

Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings (2012)

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DOI: 10.1109/TCAD.2012.2192478

access: closed

type: Journal Article

metadata version: 2020-09-24

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Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings:
FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1305-1318 (2012)

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