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"A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input ..."

Dae Hyun Kwon et al. (2019)

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DOI: 10.1109/TCSII.2018.2855692

access: closed

type: Journal Article

metadata version: 2020-05-27

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  - https://dblp.org/rec/journals/tcas/KwonKKC19
Dae Hyun Kwon, Minkyu Kim, Sung-Geun Kim, Woo-Young Choi:
A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 362-366 (2019)

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