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"An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS."

Dengquan Li et al. (2020)

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DOI: 10.1109/TCSII.2020.2968457

access: closed

type: Journal Article

metadata version: 2020-12-17

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  - https://dblp.org/rec/journals/tcas/LiLZMDZ20
Dengquan Li, Maliang Liu, Lei Zhao, Henghui Mao, Ruixue Ding, Zhangming Zhu:
An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS. IEEE Trans. Circuits Syst. 67-II(11): 2307-2311 (2020)

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