"Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital ..."

Moxiao Lou et al. (2025)

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DOI: 10.1109/TCSII.2025.3583043

access: closed

type: Journal Article

metadata version: 2025-11-18

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Moxiao Lou, Jin Wang, Humiao Li, Zhengke Yang, Quan Cheng, Jiamin Li, Masanori Hashimoto, Longyang Lin:
Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 72(11): 1605-1609 (2025)

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