"A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for ..."

Jinjia Zhou et al. (2018)

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DOI: 10.1109/TCSVT.2016.2614124

access: closed

type: Journal Article

metadata version: 2020-08-25

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Jinjia Zhou, Dajiang Zhou, Shuping Zhang, Shinji Kimura, Satoshi Goto:
A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC. IEEE Trans. Circuits Syst. Video Technol. 28(2): 556-560 (2018)

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