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"Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip ..."

Rakesh Pandey, Aryabartta Sahu (2021)

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DOI: 10.1109/TETC.2019.2946887

access: closed

type: Journal Article

metadata version: 2021-12-15

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Rakesh Pandey, Aryabartta Sahu:
Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip Multiprocessor with Hybrid Interconnect. IEEE Trans. Emerg. Top. Comput. 9(4): 1945-1959 (2021)

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